Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM

Can Wang, Junhao Ma, Yikai Wang, Shan Shen, Wei W. Xing

SRAM's power-performance-area-stability trade-off depends on bitcell topology, a discrete architectural choice that interacts non-separably with continuous transistor sizing. However, no open-source SRAM tool treats topology as an optimizable variable. OpenRAM generates SRAM layouts but performs no optimization, while OpenYield supports high-fidelity evaluation but restricts optimization to scalar sizing of a fixed 6T cell. OpenYieldV2 closes this gap through three integrated contributions. First, a fully parameterized compiler generates complete 6T and 10T SRAM macros with peripheral circuits and replica-bitline self-timing, enabling topology comparison under identical simulation conditions. Second, a few-shot TabPFN surrogate learns topology-dependent PPA responses with limited full-macro SPICE samples. Third, a coarse-to-refined multi-objective optimizer combines global exploration of discrete architectural choices with local refinement of continuous transistor sizes. Experiments across varying design conditions reveal a topology decision boundary that shifts with operating constraints rather than following a fixed design rule. Jointly optimizing across this boundary improves…